1. Field of the Invention
This invention relates to memory devices incorporated in wafer scale integrated circuits.
2. Related Art
In integrated circuit fabrication, a single crystal is generally formed and then sliced into wafers. Each wafer is then processed using conventional fabrication techniques to form an array of identical integrated circuits, and the array is then cut into pieces on each of which is one of the integrated circuits.
Because of the variability of fabrication techniques, the yield of working integrated circuits rarely approaches 100%. After testing, circuits which do not work are not used.
Recently, interest has grown in wafer scale circuits; that is, integrated circuits which make up the whole or a substantial part of the area of a wafer. A very large number of circuit components can be manufactured on a wafer, with the connections between the components provided in the fabrication process so that the distance between adjacent components is small and communications between components on the wafer are fast. However, parts of the wafer will almost certainly be defective, and the defects will vary from wafer to wafer. It is therefore necessary for wafer scale circuits to be tolerant of such defects if they are to be usable. For this reason, to date, only very limited use has been made of wafer scale circuits.
One strategy for providing fault tolerant wafer scale circuits, as discussed in our earlier International application no. WO89/07298, is to provide that the circuit comprises an array of a large number of similar components interconnected by a communications network, and to carry out a test to determine which of the components and which parts of the network are not working. WO83/02019 proposes a wafer device comprising a plurality of cells (which can be memory cells) which are tested to establish their operating condition.
It has also been proposed to utilise wafer scale integrated circuits to provide an array of data processors on a large scale, to deal with parallel processing algorithms. Our above referenced application describes one approach, and another is described in "An Interconnection Scheme for a Tightly Coupled Massively Parallel Computer Network", J D Harris and A G T Connell, Proc IEEE International Conference on computer design: VLSI in computers, ICCD'85, PP612-616.
The prior art generally employs packet switching techniques in which messages are transmitted in separate packets.